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职位名称 职位类型 工作地点 操作

Position Description:

The SiEngine technology is co-funded by Geely Group and ARM China Company. This position will be responsible for the FPGA prototyping and SoC validation work for the ARM based processor targeting the market of the automotive SoC solution.  The candidate is required to be working closely with SoC design/verification, platform design and validation team and work out the solution including the FPGA prototyping, emulation and simulation to validate our SoC.

The engineer will be working in the SiEngine R&D SW/VI team.

Main Responsibility:
- FPGA functional design with Verilog or VHDL
- FPGA simulation and verification strategy planning and architecture design
- Porting ASIC to Z1/Zebu platform and provide support and maintain
- Porting ASIC to FPGA, generate/run/debug test cases on FPGA
- Build up and maintain FPGA test platforms, including PCB schematic design and layout support

Required Skills:

- More than 2 years working experience on FPGA design and verification
- Good Knowledge on FPGA design process, knowledge on verification methodology, UVM is a plus
- Solid knowledge on ARM architectures (Core: A, R or M, MMU, SMMU, GIC, Interconnection)
- Familiar with System Verilog, VHDL is a plus
- Be familiar with any standard HW protocol and interfaces and IO standards such as PCIe, MIPI CSI/DSI, DP, SERDES, I2C, SGMII, USB, DDR, AMBA, EBI, EMIF, RapidIO.
- Familiar with board design and schematic
- Good experience in using high-speed oscilloscope, logic analyzer or other protocol analyzer.
- Experience in VCS/Palladium Z1/X1/Zebu/FPGA/Trace32 is a plus.
- Familiar with Git/Gerrit source code management tool.
- Excellent communication skills, good teamwork adaptability, self-motivated.

Education Requirement:

- B. Sc. or above degree from China top universities with major on Computer Science, EE or Automation etc.

Position Description:

The SiEngine technology is co-funded by Geely Group and ARM China Company. This position will be responsible for the FPGA prototyping and SoC validation work for the ARM based processor targeting the market of the automotive SoC solution.  The candidate is required to be working closely with SoC design/verification, platform design and validation team and work out the solution including the FPGA prototyping, emulation and simulation to validate our SoC.

The engineer will be working in the SiEngine R&D SW/VI team.


Main Responsibility:
- FPGA functional design with Verilog or VHDL
- FPGA simulation and verification strategy planning and architecture design
- Porting ASIC to Z1/Zebu platform and provide support and maintain
- Porting ASIC to FPGA, generate/run/debug test cases on FPGA
- Build up and maintain FPGA test platforms, including PCB schematic design and layout support

Required Skills:

- More than 2 years working experience on FPGA design and verification
- Good Knowledge on FPGA design process, knowledge on verification methodology, UVM is a plus
- Solid knowledge on ARM architectures (Core: A, R or M, MMU, SMMU, GIC, Interconnection)
- Familiar with System Verilog, VHDL is a plus
- Be familiar with any standard HW protocol and interfaces and IO standards such as PCIe, MIPI CSI/DSI, DP, SERDES, I2C, SGMII, USB, DDR, AMBA, EBI, EMIF, RapidIO.
- Familiar with board design and schematic
- Good experience in using high-speed oscilloscope, logic analyzer or other protocol analyzer.
- Experience in VCS/Palladium Z1/X1/Zebu/FPGA/Trace32 is a plus.
- Familiar with Git/Gerrit source code management tool.
- Excellent communication skills, good teamwork adaptability, self-motivated.

Education Requirement:

- B. Sc. or above degree from China top universities with major on Computer Science, EE or Automation etc.

Position Description:

The SiEngine technology is co-funded by Geely Group and ARM China Company. This position will be responsible for the software development of Linux kernel driver and user space reference application for the ARM based processor targeting the market of the automotive SoC solution.  The candidate is required to design and work out the solution from the Linux kernel device driver, SDK and the reference application.

The engineer will be working in the SiEngine R&D SW team.


Main Responsibility:
- Develop the bootloader, Linux kernel driver and test application for the SiEngine automotive SoC.
- Develop the software to enable and validate the driver.
- Build the automation validation framework (SLT) to validate/test the SoC and Linux.
- Develop the board support package and the reference application.

Required Skills:

- 5+ years of software development in automotive, embedded system or mobile.
- At least 2-years of experience in writing low-level software that interacts directly with hardware.
- Solid knowledge on ARM architectures (Core: A, R or M, MMU, SMMU, GIC, Interconnection)
- Good experience in Linux driver development is a must.
- Good experience in using/customizing the opensource software.
- Familiar with bootloader such as ARM trusted firmware, u-boot etc.
- Experience in open source software such as buildroot, yacto, busybox, etc.
- Experience in LSIO driver such as UART/I2C/SPI/GPIO/PWM/SD/MMC is preferred.
- Experience in Linux kernel memory management, power management (DVFS, PSCI, STR) is a plus.
- Experience in HSIO driver such as PCIE/USB2/USB3/ETH/V2L4(CSI)/UFS/DRM(DSI, DP) is a big plus.
- Familiar with Git/Gerrit source code management tool.
- Familiar with scripts such as bash, python, etc.
- Excellent communication skills, good teamwork adaptability, self-motivated.


Education Requirement:

- B. Sc. or above degree from China top universities with major on Computer Science, EE or Automation etc.

Position Description:

The SiEngine technology is co-funded by Geely Group and ARM China Company. This position will be responsible for the software development of Linux kernel driver and user space reference application for the ARM based processor targeting the market of the automotive SoC solution.  The candidate is required to design and work out the solution from the Linux kernel device driver, SDK and the reference application.

The engineer will be working in the SiEngine R&D SW team.


Main Responsibility:
- Develop the bootloader, Linux kernel driver and test application for the SiEngine automotive SoC.
- Develop the software to enable and validate the driver.
- Build the automation validation framework (SLT) to validate/test the SoC and Linux.
- Develop the board support package and the reference application.

Required Skills:

- 5+ years of software development in automotive, embedded system or mobile.
- At least 2-years of experience in writing low-level software that interacts directly with hardware.
- Solid knowledge on ARM architectures (Core: A, R or M, MMU, SMMU, GIC, Interconnection)
- Good experience in Linux driver development is a must.
- Good experience in using/customizing the opensource software.
- Familiar with bootloader such as ARM trusted firmware, u-boot etc.
- Experience in open source software such as buildroot, yacto, busybox, etc.
- Experience in LSIO driver such as UART/I2C/SPI/GPIO/PWM/SD/MMC is preferred.
- Experience in Linux kernel memory management, power management (DVFS, PSCI, STR) is a plus.
- Experience in HSIO driver such as PCIE/USB2/USB3/ETH/V2L4(CSI)/UFS/DRM(DSI, DP) is a big plus.
- Familiar with Git/Gerrit source code management tool.
- Familiar with scripts such as bash, python, etc.
- Excellent communication skills, good teamwork adaptability, self-motivated.

Education Requirement:

- B. Sc. or above degree from China top universities with major on Computer Science, EE or Automation etc.

Position Description:

The SiEngine technology is co-funded by Geely Group and ARM China Company. This position will be responsible for the development of AI SDK framework software on the ARM based processor targeting the market of the automotive SoC solution.  The candidate is required to develop the NN inference framework on Android or embedded Linux platform based on the SiEngine Soc.

The engineer will be working in the SiEngine R&D SW team.


Main Responsibility:
- Develop the NN inference  framework on Android, which is integrated with NN API.
- Develop the NN inference framework on embedded Linux.
- Develop the NPU, GPU, CPU backend running driver for NN inference framework.
- Work closely with the AI Application software engineer to extend the NN compute operator.

Required Skills:

- 5+ years of software development in automotive, embedded system or mobile.
- At least 2-years of experience in Android NDK, HAL development work, or embedded Linux Midware development work.
- Solid knowledge on ARM architectures (Core: A, R or M)
- Solid programming skill in C/C++ (above C++ 11).
- Good experience in C++ big project development.
- Good knowledge in NPU GPU, CPU SIMD parallel computing is required.
- Familiar with OpenCL, OpenVX, Neon parallel programming for NPU, GPU, CPU
- Experience in deep learning framework, like TensorFlow/PyTorch/Caffe is good plus.
- Experience in machine learning/deep learning algorithms is plus.

- Knowledge in FuSa ISO 26262 is plus.
- Familiar with Git/Gerrit source code management tool.
- Excellent communication skills, good teamwork adaptability, self-motivated.

Education Requirement:

- B. Sc. or above degree from China top universities with major on Computer Science, EE or Automation etc.

Position Description:

The SiEngine technology is co-funded by Geely Group and ARM China Company. This position will be responsible for the development of AI SDK framework software on the ARM based processor targeting the market of the automotive SoC solution.  The candidate is required to develop the NN inference framework on Android or embedded Linux platform based on the SiEngine Soc.

The engineer will be working in the SiEngine R&D SW team.


Main Responsibility:
- Develop the NN inference  framework on Android, which is integrated with NN API.
- Develop the NN inference framework on embedded Linux.
- Develop the NPU, GPU, CPU backend running driver for NN inference framework.
- Work closely with the AI Application software engineer to extend the NN compute operator.


Required Skills:

- 5+ years of software development in automotive, embedded system or mobile.
- At least 2-years of experience in Android NDK, HAL development work, or embedded Linux Midware development work.
- Solid knowledge on ARM architectures (Core: A, R or M)
- Solid programming skill in C/C++ (above C++ 11).
- Good experience in C++ big project development.
- Good knowledge in NPU GPU, CPU SIMD parallel computing is required.
- Familiar with OpenCL, OpenVX, Neon parallel programming for NPU, GPU, CPU
- Experience in deep learning framework, like TensorFlow/PyTorch/Caffe is good plus.
- Experience in machine learning/deep learning algorithms is plus.

- Knowledge in FuSa ISO 26262 is plus.
- Familiar with Git/Gerrit source code management tool.
- Excellent communication skills, good teamwork adaptability, self-motivated.

Education Requirement:

- B. Sc. or above degree from China top universities with major on Computer Science, EE or Automation etc.

Position Description:

The SiEngine technology is co-funded by Geely Group and ARM China Company. This position will be responsible for the board enablement and SoC validation work for the ARM based processor targeting the market of the automotive SoC solution.  The candidate is required to be working closely with SoC design/verification, platform design and product team and work out the solution from the bare-metal, device driver to automation framework to validate our SoC.

The engineer will be working in the SiEngine R&D SW team.


Main Responsibility:
- Develop the bare metal driver to bringup and validate the SiEngine automotive SoC.
- Develop the software to enable and validate the development boards.
- Build the automation validation framework (SLT) to validate/test the SoC.
- Develop the tools for the SoC and board manufacture.
- Evaluate the power/current/frequency of SoC with the different corner(skew) chips

Required Skills:

- 5+ years of software development in automotive, embedded system or mobile.
- At least 2-years of experience in writing low-level software that interacts directly with hardware.
- Solid knowledge on ARM architectures (Core: A, R or M, MMU, SMMU, GIC, Interconnection)
- Experience in driver development or experience in Linux driver development is a plus.
- Familiar with bootloader, Linux and any RTOS
- Familiar with board design and schematic
- Good experience in using high-speed oscilloscope, logic analyzer or other protocol analyzer.
- Experience in LSIO such as UART/I2C/SPI/GPIO/PWM/SD/MMC is preferred.
- Experience in VCS/Palladium Z1/X1/Zebu/FPGA/Trace32/System Verilog/UVM is a plus.
- Experience in HSIO such as DDR/PCIE/USB/ETH/MIPI (CSI, DSI)/UFS/DP is a big plus.
- Familiar with Git/Gerrit source code management tool.
- Familiar with scripts such as bash, python, etc.
- Excellent communication skills, good teamwork adaptability, self-motivated.

Education Requirement:

- B. Sc. or above degree from China top universities with major on Computer Science, EE or Automation etc.

Position Description:

The SiEngine technology is co-funded by Geely Group and ARM China Company. This position will be responsible for the board enablement and SoC validation work for the ARM based processor targeting the market of the automotive SoC solution.  The candidate is required to be working closely with SoC design/verification, platform design and product team and work out the solution from the bare-metal, device driver to automation framework to validate our SoC.

The engineer will be working in the SiEngine R&D SW team.


Main Responsibility:
- Develop the bare metal driver to bringup and validate the SiEngine automotive SoC.
- Develop the software to enable and validate the development boards.
- Build the automation validation framework (SLT) to validate/test the SoC.
- Develop the tools for the SoC and board manufacture.
- Evaluate the power/current/frequency of SoC with the different corner(skew) chips

Required Skills:

- 5+ years of software development in automotive, embedded system or mobile.
- At least 2-years of experience in writing low-level software that interacts directly with hardware.
- Solid knowledge on ARM architectures (Core: A, R or M, MMU, SMMU, GIC, Interconnection)
- Experience in driver development or experience in Linux driver development is a plus.
- Familiar with bootloader, Linux and any RTOS
- Familiar with board design and schematic
- Good experience in using high-speed oscilloscope, logic analyzer or other protocol analyzer.
- Experience in LSIO such as UART/I2C/SPI/GPIO/PWM/SD/MMC is preferred.
- Experience in VCS/Palladium Z1/X1/Zebu/FPGA/Trace32/System Verilog/UVM is a plus.
- Experience in HSIO such as DDR/PCIE/USB/ETH/MIPI (CSI, DSI)/UFS/DP is a big plus.
- Familiar with Git/Gerrit source code management tool.
- Familiar with scripts such as bash, python, etc.
- Excellent communication skills, good teamwork adaptability, self-motivated.

Education Requirement:

- B. Sc. or above degree from China top universities with major on Computer Science, EE or Automation etc.

Job Description
As part of the SoC design team, engineer will mainly focus on following areas, but not limited to:
-Prepare micro-architecture specification for IP, subsystem or chip;
-RTL implementation and perform integration into SOCs.
-3rd party IP configuration , optimization
-Subsystem design with in-house design and 3rd party IP
-Subsystem implementation, including synthesis/linting/cdc/DCG flow/…
-Assist with backend team on perform place-and-route and timing analysis of modules
-Assist with chip bring up and perform silicon functional/performance validation.

Job Requirement
- M.Sc. or Ph.D. degree in electrical engineering, computer engineering or equal
- Good background in C, Verilog, SystemVerilog and verification methodology.
- A high-level of self-motivation and a proactive approach to solving problems
Job Description
As part of the SoC design team, engineer will mainly focus on following areas, but not limited to:
-Prepare micro-architecture specification for IP, subsystem or chip;
-RTL implementation and perform integration into SOCs.
-3rd party IP configuration , optimization
-Subsystem design with in-house design and 3rd party IP
-Subsystem implementation, including synthesis/linting/cdc/DCG flow/…
-Assist with backend team on perform place-and-route and timing analysis of modules
-Assist with chip bring up and perform silicon functional/performance validation.

Job Requirement
- M.Sc. or Ph.D. degree in electrical engineering, computer engineering or equal
- Good background in C, Verilog, SystemVerilog and verification methodology.
- A high-level of self-motivation and a proactive approach to solving problems
Job Description
As part of the SoC design team, engineer will mainly focus on following areas, but not limited to:
-Prepare micro-architecture specification for IP, subsystem or chip;
-RTL implementation and perform integration into SOCs.
-3rd party IP configuration , optimization
-Subsystem design with in-house design and 3rd party IP
-Subsystem implementation, including synthesis/linting/cdc/DCG flow/…
-Assist with backend team on perform place-and-route and timing analysis of modules
-Assist with chip bring up and perform silicon functional/performance validation.

Job Requirement
- M.Sc. or Ph.D. degree in electrical engineering, computer engineering or equal
- Good background in C, Verilog, SystemVerilog and verification methodology.
- A high-level of self-motivation and a proactive approach to solving problems
ob Description

1. Responsible for Front-End implementation work from RTL2Netlist, including SDC/UPF/Synthesis/STA/FM/Lint/CDC. (Professional Direction)
1. 负责ASIC前端设计实现工作(RTL -> 网表),包括:时序&功耗约束/综合设计/时序分析/形式验证/RTL语法&跨时钟域检查。 (专家方向)

2. Responsible for DFT work, including Lbist/Mbist/Scan/ATPG/Boundary Scan design & simulation.
2. 负责DFT相关的工作,包括:上电自测试/memory 测试/SCAN 测试/边界测试的设计以及仿真工作。

3. Responsible for ASIC design flow development & optimization.
3. 负责搭建ASIC 设计实现/DFT的flow,以及优化。

4. Closely co-work timing & power closure with P&R.
4. 和后端一起合作,实现时序和功耗的收敛。


Job Requirement
1. Understand ASIC design flow. Basic knowledge including Synthesis/STA/FM/CDC is a plus.
1. 了解ASIC设计流程。如果了解“综合/时序分析/形式验证/跨时钟域设计”中的其中一项是加分项。

2. Basic knowledge including LEC/SDC/UPF/DFT is a plus.
2. 如果了解“时序约束/功耗约束/DFT设计”中的其中一项是加分项。

3. Familiar with unix/linux and scripts (python, tcl, perl, makefile etc.) is a plus.
3. 熟悉“unix/linux,Python/TCL/Perl/Makefile”中的其中一项是加分项。

4. Familiar with front-end EDA tools and flows is a plus.
4. 熟悉前端EDA设计工具是加分项。

5. A high-level of self-motivation and a proactive approach to solving problems.
5. 高度的自我激励和主动解决问题的意愿。
ob Description

1. Responsible for Front-End implementation work from RTL2Netlist, including SDC/UPF/Synthesis/STA/FM/Lint/CDC. (Professional Direction)
1. 负责ASIC前端设计实现工作(RTL -> 网表),包括:时序&功耗约束/综合设计/时序分析/形式验证/RTL语法&跨时钟域检查。 (专家方向)

2. Responsible for DFT work, including Lbist/Mbist/Scan/ATPG/Boundary Scan design & simulation.
2. 负责DFT相关的工作,包括:上电自测试/memory 测试/SCAN 测试/边界测试的设计以及仿真工作。

3. Responsible for ASIC design flow development & optimization.
3. 负责搭建ASIC 设计实现/DFT的flow,以及优化。

4. Closely co-work timing & power closure with P&R.
4. 和后端一起合作,实现时序和功耗的收敛。


Job Requirement
1. Understand ASIC design flow. Basic knowledge including Synthesis/STA/FM/CDC is a plus.
1. 了解ASIC设计流程。如果了解“综合/时序分析/形式验证/跨时钟域设计”中的其中一项是加分项。

2. Basic knowledge including LEC/SDC/UPF/DFT is a plus.
2. 如果了解“时序约束/功耗约束/DFT设计”中的其中一项是加分项。

3. Familiar with unix/linux and scripts (python, tcl, perl, makefile etc.) is a plus.
3. 熟悉“unix/linux,Python/TCL/Perl/Makefile”中的其中一项是加分项。

4. Familiar with front-end EDA tools and flows is a plus.
4. 熟悉前端EDA设计工具是加分项。

5. A high-level of self-motivation and a proactive approach to solving problems.
5. 高度的自我激励和主动解决问题的意愿。
ob Description

1. Responsible for Front-End implementation work from RTL2Netlist, including SDC/UPF/Synthesis/STA/FM/Lint/CDC. (Professional Direction)
1. 负责ASIC前端设计实现工作(RTL -> 网表),包括:时序&功耗约束/综合设计/时序分析/形式验证/RTL语法&跨时钟域检查。 (专家方向)

2. Responsible for DFT work, including Lbist/Mbist/Scan/ATPG/Boundary Scan design & simulation.
2. 负责DFT相关的工作,包括:上电自测试/memory 测试/SCAN 测试/边界测试的设计以及仿真工作。

3. Responsible for ASIC design flow development & optimization.
3. 负责搭建ASIC 设计实现/DFT的flow,以及优化。

4. Closely co-work timing & power closure with P&R.
4. 和后端一起合作,实现时序和功耗的收敛。


Job Requirement
1. Understand ASIC design flow. Basic knowledge including Synthesis/STA/FM/CDC is a plus.
1. 了解ASIC设计流程。如果了解“综合/时序分析/形式验证/跨时钟域设计”中的其中一项是加分项。

2. Basic knowledge including LEC/SDC/UPF/DFT is a plus.
2. 如果了解“时序约束/功耗约束/DFT设计”中的其中一项是加分项。

3. Familiar with unix/linux and scripts (python, tcl, perl, makefile etc.) is a plus.
3. 熟悉“unix/linux,Python/TCL/Perl/Makefile”中的其中一项是加分项。

4. Familiar with front-end EDA tools and flows is a plus.
4. 熟悉前端EDA设计工具是加分项。

5. A high-level of self-motivation and a proactive approach to solving problems.
5. 高度的自我激励和主动解决问题的意愿。
ob Description
As part of the SoC design team, engineer will mainly focus on following areas, but not limited to:
-Prepare micro-architecture specification for IP, subsystem or chip;
-RTL implementation and perform integration into SOCs.
-3rd party IP configuration , optimization
-Subsystem design with in-house design and 3rd party IP
-Subsystem implementation, including synthesis/linting/cdc/DCG flow/…
-Assist with backend team on perform place-and-route and timing analysis of modules
-Assist with chip bring up and perform silicon functional/performance validation.

Job Requirement
- M.Sc. or Ph.D. degree in electrical engineering, computer engineering or equal
- Good background in C, Verilog, SystemVerilog and verification methodology.
- A high-level of self-motivation and a proactive approach to solving problems

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